BI=INACTIVE, TEMT=VALID, PE=INACTIVE, RXFE=NOERROR, FE=INACTIVE, THRE=VALID, RDR=EMPTY, OE=INACTIVE
Line Status Register. Contains flags for transmit and receive status, including line errors.
| RDR | Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty. 0 (EMPTY): The UART1 receiver FIFO is empty. 1 (NOTEMPTY): The UART1 receiver FIFO is not empty. |
| OE | Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost. 0 (INACTIVE): Overrun error status is inactive. 1 (ACTIVE): Overrun error status is active. |
| PE | Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO. 0 (INACTIVE): Parity error status is inactive. 1 (ACTIVE): Parity error status is active. |
| FE | Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO. 0 (INACTIVE): Framing error status is inactive. 1 (ACTIVE): Framing error status is active. |
| BI | Break Interrupt. When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO. 0 (INACTIVE): Break interrupt status is inactive. 1 (ACTIVE): Break interrupt status is active. |
| THRE | Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write. 0 (VALID): THR contains valid data. 1 (THR_IS_EMPTY_): THR is empty. |
| TEMT | Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data. 0 (VALID): THR and/or the TSR contains valid data. 1 (EMPTY): THR and the TSR are empty. |
| RXFE | Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO. 0 (NOERROR): RBR contains no UART1 RX errors or FCR[0]=0. 1 (ERRORS): UART1 RBR contains at least one UART1 RX error. |
| RESERVED | Reserved, the value read from a reserved bit is not defined. |